分享:Cadence OrCAD and Allegro 17.20.033 Hotfix

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所属分类:pcb设计

分享:Cadence OrCAD and Allegro 17.20.033 Hotfix

Fixed CCRs: SPB 17.2 HF033
01-25-2018
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CCRID Product ProductLevel2 Title
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1828672 ADW ADWSERVER LDAP connection error while trying to log in to DBeditor
1840699 ADW DBEDITOR Unable to release footprint model due to older version being linked to a DE-HDL Block Model
1852402 ALLEGRO_EDITOR DATABASE Cutouts are not converted correctly when opening release 16.6 board in release 17.2-2016
1855223 ALLEGRO_EDITOR DATABASE Release 16.6. BoardOutline not fully converted to release 17.2-2016 Cutout Layer
1855252 ALLEGRO_EDITOR DATABASE Unable to open a previously saved release 17.2-2016 database
1863025 ALLEGRO_EDITOR DRC_CONSTR Shape voiding to Via pad with backdrill keepout is oversizing the Dynamic shape void by the backdrill keepout
1854087 ALLEGRO_EDITOR EDIT_ETCH Sliding arc crashes PCB Editor
1840667 ALLEGRO_EDITOR INTERACTIV Choosing 'Change Text block to' from pop-up displays message 'E- (SPMHGE-150): Text font is not defined'
1849133 ALLEGRO_EDITOR INTERACTIV On choosing 'Change Text block to' on text , 'Text font is not defined' message appears
1854695 ALLEGRO_EDITOR MANUFACT PCB Editor crashes while performing nc_route
1854634 ALLEGRO_EDITOR NC NC Drill file is generated with half the number of Drill Holes on enabling 'Optimize drill head travel'
1856773 ALLEGRO_EDITOR NC Issue with Optimize Drill head travel in hotfix 031: Missing drill holes
1860876 ALLEGRO_EDITOR NC NC route critical difference between hotfix 031 and 022: No slots found warning
1758671 ALLEGRO_EDITOR OTHER Export parameters takes long time to export and some times the process hangs
1040989 ALLEGRO_EDITOR SHAPE PCB Editor crashes while editing board outline
1328385 ALLEGRO_EDITOR SHAPE Check for missing thermal reliefs when shapes overlap
1366376 ALLEGRO_EDITOR SHAPE Thermal created for Xhatch shape overlapping another shape, but not created when solid shapes overlap
1716436 ALLEGRO_EDITOR SHAPE Acute angle trim should not violate DRC.
1822377 ALLEGRO_EDITOR SHAPE Setting shape parameter Acute angle trim control to Full round produces unwanted shape to keepout DRCs
1826436 ALLEGRO_EDITOR SHAPE Same net shape to hole spacing not voiding shape for cline of different net moved close to vias of same net shapes
1834510 ALLEGRO_EDITOR SHAPE Same Net Shape to Via Spacing does not always clear correctly
1850716 ALLEGRO_EDITOR SHAPE 'DiffPair combined void for vias added with Return Path option' does not work with fillet and pad suppression
1852814 ALLEGRO_EDITOR SHAPE Thermal reliefs are not created after placing modules.
1853453 ALLEGRO_EDITOR SHAPE Route keepout clipping of cross-hatched shapes needs to be corrected
1859391 ALLEGRO_EDITOR SHAPE Shapes are not using 'minimum aperture for gap width' for voiding after back drill update.
1859410 ALLEGRO_EDITOR SHAPE Shape to Teardrop is not using same net spacing rules
1825397 ALLEGRO_EDITOR UI_FORMS Option panel disappears in release 17.2-2016
1854070 ALLEGRO_EDITOR UI_GENERAL enable_command_window_history prevents many aliases and commands from working correctly
1855180 ALLEGRO_EDITOR UI_GENERAL Comma and dot do not work in funckey if 'enable_command_window_history' is set
1860003 ALLEGRO_EDITOR UI_GENERAL Icons and features missing or behaving differently in release 17.2-2016, Hotfix 031
1861278 ALLEGRO_EDITOR UI_GENERAL Icons and menus missing in PCB Editor in release 17.2-2016, Hotfix 031
1862292 ALLEGRO_EDITOR UI_GENERAL Layout Pins icon missing in toolbar in Symbol Editor since Hotfix 031
1793284 ALLEGRO_PROD_TOOLB CORE Limit View (V1R, V2R, COM) for OUTLINE layer.
1712701 ALTM_TRANSLATOR CAPTURE Third-party translator shows error for missing operand
1802182 ALTM_TRANSLATOR CAPTURE Imported schematic has connectivity loss
1802462 ALTM_TRANSLATOR CAPTURE Hierarchical ports placed incorrectly for imported third-party design
1823935 ALTM_TRANSLATOR CAPTURE Translating third-party schematics with hierarchical pages from Design Entry CIS
1830570 ALTM_TRANSLATOR CAPTURE Third-party to Capture translation is translating only one page out of 32
1839627 ALTM_TRANSLATOR CAPTURE Third-party translator is not importing complete schematic
1846965 ALTM_TRANSLATOR CAPTURE Cannot translate third-party schematic
1816767 ALTM_TRANSLATOR DE_HDL Error when translating third-party schematic to DE-HDL
1845601 ALTM_TRANSLATOR PCB_EDITOR Cannot operate third-party PCB translation in release 17.2-2016 Allegro Venture PCB Designer license
1841060 APD DIE_GENERATOR Cannot 'die text out' from SiP Layout or Allegro Package Designer
1793232 APD SHAPE When fillet/taper not connected to a pin, voiding process incorrectly applies shape clearance values
1846541 APD SHAPE shape degassing does not obey void to shape boundary
1863446 ASDA CONSTRAINT_MA A space in the name of a spacing or physical constraint results in the incorrect constraint set name
1859678 ASDA VARIANT_MANAG SDA - When hovering over all three buttons, under Preferred Parts in the Variant info it says (Do not install)
1815839 CONCEPT_HDL CORE Allegro Design Entry HDL crashes when entering Location data manually
1841857 CONCEPT_HDL CORE Unable to modify Components in non-windows mode
1852096 CONCEPT_HDL CORE Creating a block using top-down approach does not generate the CSB file
1857390 CONCEPT_HDL CORE DE-HDL crashes on moving symbol
1789070 CONCEPT_HDL OTHER Having folder 'allegro' in cpm root directory gives error while launching layout editor from Project Manager
1862484 CONSTRAINT_MGR CONCEPT_HDL Extracting an ECSet in SigXP is missing a t-point
1863045 CONSTRAINT_MGR CONCEPT_HDL Pin pairs deleted for a few differential pairs after upreving the design to release 17.2-2016
1863054 CONSTRAINT_MGR CONCEPT_HDL Differential Pairs are treated as invalid objects on upreved design
1863094 CONSTRAINT_MGR CONCEPT_HDL Pin-Pairs are shown duplicated in the topology for the extracted object (Diff Pair)
1831998 CONSTRAINT_MGR OTHER 'Tools - Options' settings not saved on closing Constraint Manager
1855324 CONSTRAINT_MGR OTHER Enable the option 'Expand Hierarchy' in 'Find and Replace' dialog, by default
1860847 CONSTRAINT_MGR OTHER 'Include Routed interconnect' option once enabled, should remain enabled for that board file
1843359 EAGLE_TRANSLATOR PCB_EDITOR While importing third-party PCB, many footprints do not convert, even though the log file says footprint created
1839978 SCM REPORTS dsreportgen unable to output reference designator from a lower-level hierarchical block if it has a single component
1850013 SIP_LAYOUT OTHER Environment variable 'icp_disable_cte_auto_update' needs grammatical change
1833742 SIP_LAYOUT PADSTACK_EDIT When creating Die to Die Via using Generate Padstacks, resultant pad stack has wrong Layers
1619098 SIP_LAYOUT SHAPE Acute angle of shape in design
1728628 SIP_LAYOUT SHAPE Auto-void in dynamic shape does not disappear if object is removed
1854592 SIP_LAYOUT VIA_STRUCTURE Create via structure returns an error

链接:https://pan.baidu.com/s/1bqQmTlH 密码:3mtb

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